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dc.contributor.authorSilva, Ricardo Cunha Gonçalves dapt_BR
dc.contributor.authorBoudinov, Henri Ivanovpt_BR
dc.contributor.authorCarro, Luigipt_BR
dc.date.accessioned2011-01-28T05:59:11Zpt_BR
dc.date.issued2006pt_BR
dc.identifier.issn0018-9383pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/27584pt_BR
dc.description.abstractThis brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-μm technology. The proposed logic circuits overcome the limitations of previous implementations used for multiple-valued logic circuits, such as static power consumption and noise vulnerability.en
dc.format.mimetypeapplication/pdfpt_BR
dc.language.isoengpt_BR
dc.relation.ispartofIEEE transactions on electron devices. New York. Vol. 53, n. 6 (June 2006), p. 1480-1483pt_BR
dc.rightsOpen Accessen
dc.subjectInverteren
dc.subjectMicroeletrônicapt_BR
dc.subjectMultiple-valued logic (MVL) circuitsen
dc.subjectNMAXen
dc.subjectNMINen
dc.subjectVoltage-mode quaternaryen
dc.subjectCMOS desigen
dc.titleA novel voltage-mode CMOS quaternary logic designpt_BR
dc.typeArtigo de periódicopt_BR
dc.identifier.nrb000565276pt_BR
dc.type.originEstrangeiropt_BR


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