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Constraint-driven test scheduling for NoC-based systems

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Constraint-driven test scheduling for NoC-based systems

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Título Constraint-driven test scheduling for NoC-based systems
Autor Cota, Erika Fernandes
Liu, Chunsheng
Abstract On-chip integrated network, the so-called networkon- chip (NoC), is becoming a promising communication paradigm for the next-generation embedded core-based system chips. The reuse of the on-chip network as test access mechanism has been recently proposed to handle the growing complexity of testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various constraints. Therefore, efficient test-scheduling methods are required to deliver feasible test time while meeting all the constraints. In this paper, the authors propose a comprehensive approach to test scheduling in NoC-based systems. The proposed scheduling algorithm is based on the use of dedicated routing path that is suitable for nonpreemptive test. The algorithm is improved by incorporating both preemptive and nonpreemptive tests. In addition, BIST, precedence, and power constraints were taken into consideration. Experimental results for the ITC’02 system-on-chip benchmarks show that the nonpreemptive scheduling based on dedicated path can efficiently reduce test application time compared to previous work, and the improved method provides a practical solution to the real-world NoC-based-system testing with both preemptive and nonpreemptive cores. It is also shown that various constraints can be incorporated to deliver a comprehensive test solution.
Contido em IEEE transactions on CAD of integrated circuits and systems. New York. Vol. 25, no. 11 (Nov. 2006), p. 2465-2478
Assunto Microeletronica
[en] Network-on-chip (NoC)
[en] System-on-chip (SoC) testing
[en] Test access mechanism (TAM)
[en] Test scheduling
Origem Estrangeiro
Tipo Artigo de periódico
URI http://hdl.handle.net/10183/27601
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