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Probabilistic approach for yield analysis of dynamic logic circuits

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Probabilistic approach for yield analysis of dynamic logic circuits

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Título Probabilistic approach for yield analysis of dynamic logic circuits
Autor Brusamarello, Lucas
Silva, Roberto da
Wirth, Gilson Inacio
Reis, Ricardo Augusto da Luz
Abstract In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This work proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study delay and contention time in the presence of process variability. The methodology is employed for yield analysis of two typical wide-NOR circuits: one with a static keeper and another without the keeper. Since we use a general numerical approach for the calculation of derivatives and error propagation, the proposed yield analysis methodology may be applied to a wide range of dynamic gates (for instance pre-charge dynamic gates using dynamic keeper). The proposed methodology results in errors less than 2% when compared to Monte Carlo simulation, while increasing computational efficiency up to 100 .
Contido em IEEE transactions on circuits and systems. I, Regular Papers. New York. Vol. 55, no. 8 (Sept. 2008), p. 2238-2248
Assunto Microeletronica
[en] Design for yield
[en] Monte Carlo methods
[en] Probabilistic analysis
[en] Process variability
[en] VLSI
[en] Yield estimation
Origem Estrangeiro
Tipo Artigo de periódico
URI http://hdl.handle.net/10183/27616
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