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New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors

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New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors

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Título New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors
Autor Abate, F.
Sterpone, Luca
Lisboa, Carlos Arthur Lang
Carro, Luigi
Violante, Massimo
Abstract The growing availability of embedded processors inside FPGAs provides unprecedented flexibility for system designers. The use of such devices for space or mission critical applications, however, is being delayed by the lack of effective low cost techniques to mitigate radiation induced errors. In this paper a non invasive approach for the implementation of fault tolerant systems based on COTS processors embedded in FPGAs, using lockstep in conjunction with checkpoint and rollback recovery, is presented. The proposed approach does not require modifications in the processor architecture or in the application software. The experimental validation of this approach through fault injection is described, the corresponding results are discussed, and the addition of a write history table as a means to reduce the performance overhead imposed by previous implementations is proposed and evaluated.
Contido em IEEE transactions on nuclear science. New York. Vol. 56, no 4 (Aug. 2009), p. 1992-2000
Assunto Microeletronica
Sistemas embarcados
[en] Checkpoint
[en] Embedded processors reliability
[en] Fault injection
[en] Lockstep
[en] Rollback recovery
[en] Single event effects
Origem Estrangeiro
Tipo Artigo de periódico
URI http://hdl.handle.net/10183/27627
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