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Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV

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Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV

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Título Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV
Autor Agostini, Luciano Volcan
Azevedo Filho, Arnaldo Pereira de
Staehler, Wagston Tassoni
Rosa, Vagner Santos da
Zatt, Bruno
Pinto, Ana Cristina Medina
Porto, Roger Endrigo Carvalho
Bampi, Sergio
Susin, Altamiro Amadeu
Abstract This paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.
Contido em Journal of the Brazilian Computer Society. Vol. 12, n. 4 (March 2007), p. 25-36
Assunto Codificacao : Video digital
Fpga
Sistemas digitais
Televisão digital
[en] Digital Television
[en] FPGA Prototping
[en] H.264/AVC Decoder
[en] HDTV
[en] Video Coding
[en] VLSI Architectures
Origem Nacional
Tipo Artigo de periódico
URI http://hdl.handle.net/10183/72568
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