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dc.contributor.authorAgostini, Luciano Volcanpt_BR
dc.contributor.authorAzevedo Filho, Arnaldo Pereira dept_BR
dc.contributor.authorStaehler, Wagston Tassonipt_BR
dc.contributor.authorRosa, Vagner Santos dapt_BR
dc.contributor.authorZatt, Brunopt_BR
dc.contributor.authorPinto, Ana Cristina Medinapt_BR
dc.contributor.authorPorto, Roger Endrigo Carvalhopt_BR
dc.contributor.authorBampi, Sergiopt_BR
dc.contributor.authorSusin, Altamiro Amadeupt_BR
dc.date.accessioned2013-06-19T01:43:47Zpt_BR
dc.date.issued2007pt_BR
dc.identifier.issn0104-6500pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/72568pt_BR
dc.description.abstractThis paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.en
dc.format.mimetypeapplication/pdf
dc.language.isoengpt_BR
dc.relation.ispartofJournal of the Brazilian Computer Society. Vol. 12, n. 4 (March 2007), p. 25-36pt_BR
dc.rightsOpen Accessen
dc.subjectSistemas digitaispt_BR
dc.subjectVideo Codingen
dc.subjectFpgapt_BR
dc.subjectH.264/AVC Decoderen
dc.subjectDigital Televisionen
dc.subjectTelevisão digitalpt_BR
dc.subjectCodificacao : Video digitalpt_BR
dc.subjectHDTVen
dc.subjectVLSI Architecturesen
dc.subjectFPGA Prototpingen
dc.titleDesign and FPGA prototyping of a H.264/AVC main profile decoder for HDTVpt_BR
dc.typeArtigo de periódicopt_BR
dc.identifier.nrb000597171pt_BR
dc.type.originNacionalpt_BR


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