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dc.contributor.advisorKastensmidt, Fernanda Gusmão de Limapt_BR
dc.contributor.authorAlmeida, Antonio Felipe Costa dept_BR
dc.date.accessioned2017-10-07T05:44:10Zpt_BR
dc.date.issued2014pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/169238pt_BR
dc.description.abstractThe interaction of radiation with integrated circuits can provoke transient faults due to the deposit of charge in sensitive nodes of transistors. Because of the decrease the size in the process technology, charge sharing between transistors placed close to each other has been more and more observed. This phenomenon can lead to multiple transient faults. Therefore, it is important to analyze the effect of multiple transient faults in integrated circuits and investigate mitigation techniques able to cope with multiple faults. This work investigates the effect known as single-event-induced charge sharing in integrated circuits. Two main techniques are analyzed to cope with this effect. First, a placement constraint methodology is proposed. This technique uses placement constraints in standard cell based circuits. The objective is to achieve a layout for which the Soft-Error Rate (SER) due charge shared at adjacent cell is reduced. A set of fault injection was performed and the results show that the SER can be minimized due to single-event-induced charge sharing in according to the layout structure. Results show that by using placement constraint, it is possible to reduce the error rate from 12.85% to 10.63% due double faults. Second, Triple Modular Redundancy (TMR) schemes with different levels of granularities limited by majority voters are analyzed under multiple faults. The TMR versions are implemented using a standard design flow based on a traditional commercial standard cell library. An extensive fault injection campaign is then performed in order to verify the softerror rate due to single-event-induced charge sharing in multiple nodes. Results show that the proposed methodology becomes crucial to find the best trade-off in area, performance and soft-error rate when TMR designs are considered under multiple upsets. Results have been evaluated in a case-study circuit Advanced Encryption Standard (AES), synthesized to 90nm Application Specific Integrated Circuit (ASIC) library, and they show that combining the two techniques, the error rate resulted from multiple faults can be minimized or masked. By using TMR with different granularities and placement constraint methodology, it is possible to reduce the error rate from 11.06% to 0.00% for double faults. A detailed study of triple, four and five multiple faults combining both techniques are also described. We also tested the TMR with different granularities in SRAM-based FPGA platform. Results show that the versions with a fine grain scheme (FGTMR) were more effectiveness in masking multiple faults, similarly to results observed in the ASICs. In summary, the main contribution of this master thesis is the investigation of charge sharing effects in ASICs and the use of a combination of techniques based on TMR redundancy and placement to improve the tolerance under multiple faults.pt_BR
dc.format.mimetypeapplication/pdf
dc.language.isoengpt_BR
dc.rightsOpen Accessen
dc.subjectFault toleranceen
dc.subjectMicroeletrônicapt_BR
dc.subjectPlacement Constrainingen
dc.subjectTolerancia : Falhaspt_BR
dc.subjectSingle-Event-Induced Charge Sharingen
dc.subjectTriple Modular Redundancyen
dc.titleInvestigating techniques to reduce soft error rate under single-event-induced charge sharingpt_BR
dc.title.alternativeInvestigando técnicas para reduzir a taxa de erro de soft sob evento único induzido de carga compartilhada pt_BR
dc.typeDissertaçãopt_BR
dc.identifier.nrb001047365pt_BR
dc.degree.grantorUniversidade Federal do Rio Grande do Sulpt_BR
dc.degree.departmentInstituto de Informáticapt_BR
dc.degree.programPrograma de Pós-Graduação em Microeletrônicapt_BR
dc.degree.localPorto Alegre, BR-RSpt_BR
dc.degree.date2014pt_BR
dc.degree.levelmestradopt_BR


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