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dc.contributor.advisorKlimach, Hamilton Duartept_BR
dc.contributor.authorDornelas, Helga Uchoapt_BR
dc.date.accessioned2018-12-06T02:45:35Zpt_BR
dc.date.issued2018pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/186015pt_BR
dc.description.abstractThe "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate.en
dc.format.mimetypeapplication/pdfpt_BR
dc.language.isoengpt_BR
dc.rightsOpen Accessen
dc.subjectMicroeletrônicapt_BR
dc.subjectCMOS Analog Designen
dc.subjectCmospt_BR
dc.subjectInternet of Thingsen
dc.subjectSuccessive Approximation ADCen
dc.subjectInternet das coisaspt_BR
dc.subjectLow Power Designen
dc.subjectAnalog to Digital Converteren
dc.titleLow power SAR analog-to-digital converter for internet-of-things RF receiverspt_BR
dc.title.alternativeConversor analógico-digital SAR de baixo consumo para receptores RF de internet-das-coisas pt
dc.typeDissertaçãopt_BR
dc.contributor.advisor-coFabris, Eric Ericsonpt_BR
dc.identifier.nrb001082279pt_BR
dc.degree.grantorUniversidade Federal do Rio Grande do Sulpt_BR
dc.degree.departmentInstituto de Informáticapt_BR
dc.degree.programPrograma de Pós-Graduação em Microeletrônicapt_BR
dc.degree.localPorto Alegre, BR-RSpt_BR
dc.degree.date2018pt_BR
dc.degree.levelmestradopt_BR


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