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dc.contributor.authorSwoboda, C.pt_BR
dc.contributor.authorBarsotti, E.pt_BR
dc.contributor.authorBowden, Markpt_BR
dc.contributor.authorChristian, Davidpt_BR
dc.contributor.authorDemaat, Robertpt_BR
dc.contributor.authorFachin Junior, Miguelpt_BR
dc.contributor.authorGonzalez, Hectorpt_BR
dc.contributor.authorHance, Rickpt_BR
dc.contributor.authorHaldeman, Merlept_BR
dc.contributor.authorHoff, Jimpt_BR
dc.contributor.authorLarwill, Markpt_BR
dc.contributor.authorRotolo, Carmenpt_BR
dc.contributor.authorTrendler, Robertpt_BR
dc.contributor.authorTreptow, Kenpt_BR
dc.contributor.authorUrish, Johnpt_BR
dc.contributor.authorWalsh, Donpt_BR
dc.contributor.authorYarema, Raypt_BR
dc.contributor.authorZimmerman, Tompt_BR
dc.date.accessioned2011-02-02T05:59:09Zpt_BR
dc.date.issued1990pt_BR
dc.identifier.issn0018-9499pt_BR
dc.identifier.urihttp://hdl.handle.net/10183/27639pt_BR
dc.description.abstractThis paper describes a synchronous silicon S ~rePado ut system capable of zero deadtime readout at average trigger rates in excess of 1 MHz. The system is implemented in FASTBUS, uses pipelining techniques, and includes p6nt-Wpoint fiberoptic data links to transmit detector digital data. Semi-custom ASIC chips are used to amplify, discriminate, and logically combine track data before encoding. This paper describes the overall system, each major FASTBUS module, and the functional aspects of the ASIC chips.en
dc.format.mimetypeapplication/pdf
dc.language.isoengpt_BR
dc.relation.ispartofIEEE Transactions on Nuclear Science. New York. Vol. 37, no. 2 (Apr. 1990), p. 342-346pt_BR
dc.rightsOpen Accessen
dc.subjectBandas paralelaspt_BR
dc.subjectSaida de dados digitalpt_BR
dc.titleA high-rate fastbus silicon strip readout systempt_BR
dc.typeArtigo de periódicopt_BR
dc.identifier.nrb000055062pt_BR
dc.type.originEstrangeiropt_BR


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